/*
 * Copyright : (C) 2024 Termony Technology, Inc. All Rights Reserved.
 */

#ifndef RK_SDMMC_HW_H
#define RK_SDMMC_HW_H

#ifdef __cplusplus
extern "C"
{
#endif

/** @name Register Map
 *
 * Register offsets for the SDMMC.
 */
#define RK_SDMMC_CTRL_OFFSET                0x0000U /* Control register */
#define RK_SDMMC_PWREN_OFFSET               0x0004U /* Power enable register */
#define RK_SDMMC_CLKDIV_OFFSET              0x0008U /* Clock divider register */
#define RK_SDMMC_CLKSRC_OFFSET              0x000CU /* SD clock source register */
#define RK_SDMMC_CLKENA_OFFSET              0x0010U /* Clock enable register */
#define RK_SDMMC_TMOUT_OFFSET               0x0014U /* Timeout register */
#define RK_SDMMC_CTYPE_OFFSET               0x0018U /* Card type register */
#define RK_SDMMC_BLKSIZ_OFFSET              0x001CU /* Block size register */
#define RK_SDMMC_BYTCNT_OFFSET              0x0020U /* Byte count register */
#define RK_SDMMC_INTMASK_OFFSET             0x0024U /* Interrupt mask register */
#define RK_SDMMC_CMDARG_OFFSET              0x0028U /* Command argument register */
#define RK_SDMMC_CMD_OFFSET                 0x002CU /* Command register */
#define RK_SDMMC_RESP0_OFFSET               0x0030U /* Response register 0 */
#define RK_SDMMC_RESP1_OFFSET               0x0034U /* Response register 1 */
#define RK_SDMMC_RESP2_OFFSET               0x0038U /* Response register 2 */
#define RK_SDMMC_RESP3_OFFSET               0x003CU /* Response register 3 */
#define RK_SDMMC_MINTSTS_OFFSET             0x0040U /* Masked interrupt status register */
#define RK_SDMMC_RINTSTS_OFFSET             0x0044U /* Raw interrupt status register */
#define RK_SDMMC_STATUS_OFFSET              0x0048U /* Status register */
#define RK_SDMMC_FIFOTH_OFFSET              0x004CU /* FIFO threshold register */
#define RK_SDMMC_CDETECT_OFFSET             0x0050U /* Card detect register */
#define RK_SDMMC_WRTPRT_OFFSET              0x0054U /* Write protect register */
#define RK_SDMMC_TCBCNT_OFFSET              0x005CU /* Transferred card byte count register */
#define RK_SDMMC_TBBCNT_OFFSET              0x0060U /* Transferred host to FIFO byte count register */
#define RK_SDMMC_DEBNCE_OFFSET              0x0064U /* Debounce count register */
#define RK_SDMMC_USRID_OFFSET               0x0068U /* User ID register */
#define RK_SDMMC_VERID_OFFSET               0x006CU /* Version ID register */
#define RK_SDMMC_HCON_OFFSET                0x0070U /* Hardware configuration register */
#define RK_SDMMC_UHSREG_OFFSET              0x0074U /* UHS-1 control register */
#define RK_SDMMC_RSTN_OFFSET                0x0078U /* Hardware reset register */
#define RK_SDMMC_BMOD_OFFSET                0x0080U /* Bus mode register */
#define RK_SDMMC_PLDMND_OFFSET              0x0084U /* Poll demand register */
#define RK_SDMMC_DBADDR_OFFSET              0x0088U /* Descriptor list base address register */
#define RK_SDMMC_IDSTS_OFFSET               0x008CU /* Internal DMAC status register */
#define RK_SDMMC_IDINTEN_OFFSET             0x0090U /* Internal DMAC interrupt enable register */
#define RK_SDMMC_DSCADDR_OFFSET             0x0094U /* Current host descriptor address register */
#define RK_SDMMC_BUFADDR_OFFSET             0x0098U /* Current buffer descriptor address register */
#define RK_SDMMC_CARDTHRCTL_OFFSET          0x0100U /* Card threshold control register */
#define RK_SDMMC_BACKEND_POWER_OFFSET       0x0104U /* Back-end power register */
#define RK_SDMMC_EMMCDDR_REG_OFFSET         0x010CU /* eMMC4.5 DDR start bit detection control register */
#define RK_SDMMC_RDYINT_GEN_OFFSET          0x0120U /* Card ready interrupt generation control register */
#define RK_SDMMC_FIFO_BASE_OFFSET           0x0200U /* FIFO base address register */

#ifdef __cplusplus
}
#endif

#endif /* RK_SDMMC_HW_H */